Mixed Signal IC Layout Design Engineer
Role Overview
This role involves designing full-custom layouts for high-performance analog and mixed-signal IP in advanced FinFET nodes, translating schematics into manufacturable layouts to meet performance, power, area, and reliability targets, and integrating these blocks into larger SoCs. It is suitable for candidates at various experience levels, from junior to senior, as assessed during interviews, and the engineer will work within a collaborative team focused on cutting-edge AI technology and semiconductor innovation.
Perks & Benefits
The position is fully remote based in North America, offering flexibility in work location and likely standard tech benefits such as health insurance and retirement plans. The company emphasizes a culture of collaboration, curiosity, and solving hard problems, with opportunities for career growth in a diverse team developing high-performance RISC-V CPUs and AI platforms.
Full Job Description
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is looking for a Mixed-Signal IC Layout Design Engineer to own a full‑custom layout for high‑performance analog and mixed‑signal IP in advanced FinFET nodes. You'll translate schematics into manufacturable layouts that hit aggressive performance, power, area, and reliability targets, and integrate these blocks cleanly into larger SoCs.
This role is remote, based out of North America.
We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting
Who You Are
- An experienced analog/mixed‑signal IC layout engineer with 5 years experience delivered silicon in CMOS/FinFET nodes. Deep proficiency in Cadence Virtuoso (XL/GXL) or equivalent custom layout environments, including constraint‑driven layout and PCells.
- Strong understanding of CMOS devices, interconnect stacks, and advanced‑node rules, including multi‑patterning, density/fill, and lithography‑driven constraintPlease mention the word **AFFLUENCE** and tag RODguMTk4Ljk5LjE0Mw== when applying to show you read the job post completely (#RODguMTk4Ljk5LjE0Mw==). This is a beta feature to avoid spam applicants. Companies can search these words to find applicants that read this and see they're human.
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