High-Speed Interface Test & Characterisation Engineer

About Us

Axelera AI is not your regular deep-tech startup. We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us.

In just four years, we have raised a total of $370 million and have built a world-class team of 220+ employees (including 49+ PhDs with more than 40,000 citations), both remotely from 18 different countries and with offices in Belgium, France, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands.

We have also launched our Metis™ AI Platform, which achieves a 3-5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million.

Our unwavering commitment to innovation has firmly established us as a global industry pioneer.

Are you up for the challenge?

Position Overview

We are looking for a High-Speed Interface Test & Characterisation Engineer to join our AI accelerator team at Axelera AI, based in our Bristol lab.

You will fully own the post-silicon characterisation, compliance testing, and formal certification of PCIe and LPDDR interfaces across our AIPU devices and board-level products — from first silicon bring-up through production qualification. Working hands-on with sophisticated lab equipment, you will be the technical authority on high-speed interface testing within the organisation, collaborating closely with silicon design, hardware, and software teams. Your work is what ensures our chips communicate reliably at multi-gigabit data rates in customer systems.

Why This Role Matters

At Axelera AI, PCIe and LPDDR are the critical connections between our AI accelerator cores and the outside world. No matter how well the inference engine performs, interface issues make a chip unusable. You will be the person who ensures those connections are solid — meeting the standards required for our chips to work reliably in any compliant datacentre or automotive system. This is a chance to build a world-class test capability at a growing AI hardware company, with direct influence on both current products and next-generation interface design decisions.

Key responsibilities:

• Own PCIe and LPDDR validation end-to-end: signal integrity, electrical compliance, protocol testing, and formal certification, including getting products onto the PCI-SIG integrators list.

• Execute PCIe Tx/Rx electrical compliance, protocol, and certification testing across Gen 3 through Gen 6, and perform LPDDR electrical compliance testing (eye mask, margin, and jitter analysis) for LPDDR4, LPDDR5, and LPDDR6.

• Create and execute post-silicon characterisation plans across PVT corners, designing test sequences that surface issues early and prioritise the measurements with the highest diagnostic value.

• Review signal integrity simulations from die through package and PCB, providing design-phase feedback and helping designers reconcile simulation models with post-silicon measurements.

• Work with hardware engineers to specify test boards, fixtures, and probing requirements; define and source compliance test fixtures and interposers suited to our packages.

• Collaborate with software and firmware teams to debug link stability issues, optimising initialisation sequences, training protocols, and link configuration.

• Develop Python-based test automation to drive equipment, collect data systematically, and generate reports — enabling comprehensive overnight test runs and focusing your time on analysis.

• Act as primary technical contact with external test equipment suppliers and test houses for formal certification activities.

• Produce clear, thorough validation and compliance reports documenting results, requirement comparisons, and residual risks.

• Build and maintain lab infrastructure: calibration schedules, probe libraries, standard operating procedures, and documentation that allows others to replicate your measurements.

Qualifications:

• Experience: Minimum 10 years in high-speed interface validation, with hands-on lab expertise making difficult measurements work on real silicon.

• Standards Knowledge: Deep understanding of PCIe through Gen 6 and LPDDR4/5/6 specifications, at a level sufficient to debate subtle interpretation points and explain requirements to design teams.

• Compliance Track Record: Demonstrated experience completing the full PCI-SIG certification process and successfully placing products on the integrators list.

• Lab Equipment: Extensive hands-on experience with high-bandwidth oscilloscopes and probes, compliance test applications, protocol analysers, interposers, and exercisers — knowing not just how to operate them but how to select the right tool and interpret measurement artefacts.

• Scripting: Proficiency in Python for test automation and equipment control; familiarity with SystemC for software-based testing.

• Environment: Comfortable working in Linux, navigating the command line, and managing test code in git.

• Bonus: Working knowledge of UCIe, CXL, and PAM4 modulation for emerging interface standards.

• Strong cross-functional collaboration skills — able to work effectively with silicon designers, hardware engineers, and software teams, and translate between their different technical perspectives.

Location

This position is based in Bristol on an on-site/hybrid basis,

What we offer 

This is your chance to shape and be part of a dynamic, fast-growing, international organization. We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares.   

An open culture that supports creativity and continual innovation is awaiting you. Collaborative ownership and freedom with responsibility is characteristic for the way we act and work as a team. 

At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI.